1. Field of the Invention
The present invention relates to a method and an apparatus for processing an error correction code and, more particularly, to a method and apparatus for parallelly processing data and error correction code in a memory.
2. The Related Arts
Flash memory is widely used in many digital consumer products, such as digital cameras, TV game boxes, flash drives. As the semiconductor fabrication technology improves, the capacity of flash memory also increases significantly. For example, the 32 Mb (mega bytes) flash memory chips manufactured by Samsung comprises 1024 blocks, with each block having 64 pages. In each page, there are 528(=512+16) bytes, wherein 512 bytes are the data area, and 16 bytes are the redundant area. The flash memory is typically accessed by block.
The universal serial bus (USB) ports of a PC can connect various USB devices, such as, a USB keyboard, a USB mouse, a USB card reader, a USB memory flash drive, a USB floppy drive, a USB printer and a USB scanner. The transmission speed also evolves from 12 Mbps in USB1.1 to 480 Mbps in USB2.0.
As the tranceiving speed increases, the speed for accessing the flash memory should be increased. To guarantee the correctness during the speedy access, the flash memory applies the error correction code (ECC) to make sure that the data access is intact.
FIG. 1 of the attached drawings shows a block diagram of a conventional flash memory controller, designated with reference numeral 100. The flash memory controller 100 comprises a direct memory access unit 110, a first-in-first-out (FIFO) memory 120, an ECC calculation unit 130, an exclusive-or gate 140, an I/O FIFO memory 150, and a microprocessor 160. The conventional controller 100 usually accesses the flash memory on a page basis, and generates associated ECC code. Assume that each memory page is 512+16 bytes, where 16 bytes provide a redundancy area for storing system information and associated ECC. For example, ECC is 10 bytes, the following steps show how a direct memory access unit 110 reads a page from the flash memory (not shown): (1) The direct memory access unit 110 reads 512 bytes of data into the FIFO memory 120. (2) The ECC calculation unit 130 calculates an associated syndrome using the 512 bytes data and 10 bytes ECC. (3) The exclusive-or gate 140 corrects error(s) for the 512 bytes of data using the syndrome in step (2). (4) The corrected data are outputted to I/O FIFO memory 150. Furthermore, the direct memory access unit 110 is coupled to and controlled by the microprocessor 160 for memory accessing. Conventionally, the direct memory access unit 110 cannot access the next page until the step of error correction is completed. Hence, access latency exists between the accesses to the different pages.
FIG. 2 shows the corresponding waveform of the operation in FIG. 1. The high in the data signal waveform indicates the data phase corresponding to reading 512 bytes. On the other hand, the high in the ECC signal waveform indicates the ECC phase corresponding to the accessing of the 10 bytes of ECC code. The low in the last portion of both signal waveforms indicates the access latency between accessing two different pages.